Power MOSFETs (metal oxide semiconductor (MOS) field effect transistors (FET)) are used as electric switches for high frequency PWM (pulse width modulation) applications such as voltage regulators and as load switches in general power applications. When used as load switches where switching times are usually long, cost, size and on-resistance of the switches are the prevailing design considerations. The primary concern with power devices used as load switches is low specific on resistance (Rds,on*Area). When used in PWM applications, the transistors must exhibit small power loss during switching, which imposes an additional requirement—small internal capacitances—that make the MOSFET design challenging and often times more expensive.
Vertical double diffused MOSFET (VDMOS) having vertical current flow are known in the art for medium voltage power applications, e.g., from about 50-600V. Vertical trench devices have been reported for power applications between 12-150V.
There are three popular cell geometries for the layout of VDMOS devices: stripe, square closed cell (i.e., checkerboard) and hexagonal. The stripe layout is typically preferred for power devices because it allows for smaller cell dimensions, leads to an improved avalanche ruggedness of the transistor and leads to lower specific Rds,on, as described in, for example, Anthony Murray, et al., “New Power MOSFET Technology with Extreme Ruggedness and Ultra-Low RDS(on) Qualified to Q101 for Automotive Applications,” in Proceedings of PCIM 2000 Europe, Power Conversion, paper PC 4.5, pp. 103-107, Nürnberg 2000. The conclusions made by Murray, et al. reflect the state of the art using medium to large cell pitches (e.g., 2.5 to 5 μm) typical for products designed for medium to high drain voltages (e.g., >60V). Another popular layout for these types of products uses a hexagonal cell pattern.
Prior art lateral double diffused MOSFET (LDMOS) devices have been employed for low power, high frequency applications, such as high frequency signal amplification where specific on-resistance is not a real concern. These LDMOS devices use thick epitaxial layers to achieve the breakdown voltages (>60V) required for the target RF applications. The primary concern with these high frequency devices is parasitic component values. To minimize the parasitic source inductance in the assembly, devices are designed on P+ substrates leading the source electrode to the back side of the die. The thick epitaxial layer and P+ substrate results in a high on resistance (Rds,on) in the device, which is not acceptable for power management applications as explained above. The RF devices are typically arranged in a stripe layout. This in turn leads to a de-biasing effect known for lateral devices (voltage drop along a stripe electrode under high current conditions) and limits the current handling capability of the device. Further, the shield gate tends to be laterally constrained to the space between the gate and the drain electrodes and is applicable only to a stripe layout of the drain electrode.
LDMOS devices have also been proposed as power devices for 20-30V applications. Stripe and closed cell layouts have been proposed by Andy Strachan et al., “Optimization of LDMOS Array Design for SOA and Hot Carrier Lifetime,” 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003 Proceedings, ISPSD '03. Strachan et al. conclude that the stripe cell layout is preferred for better safe operating area (SOA) and improved hot carrier reliability while keeping similar, or even lower, specific on resistance than checkerboard types of closed cell geometries. The reported reliability problems are due to the bipolar action of the parasitic NPN transistor formed by the source, body and drift regions. This transistor is triggered by the voltage drop between the P-body in the channel and the P+ contact caused by hole current from impact ionization. The way to avoid the action of the parasitic bipolar transistor is to reduce the sheet resistance Rb of the P-body so far that the voltage drop on Rb stays below 0.7V. This approach, however, is limited by the design rule requesting that a specific distance between the P+ contact and the polysilicon gate be kept larger than a minimum value defined by the technology generation, i.e., 0.5 μm for a 0.5 μm technology.
There is an ever increasing need for low voltage power devices, such as for power switches used in consumer portable electronic devices which are battery operated and do not use drain voltages exceeding 10V. As yet, the technologies described above have not met the demand for an improved specific Rds,on and size for low voltage power devices.